Three-level neutral point clamping pwn inverter and neutral point voltage controller

ABSTRACT

On the basis of: a first calculated value ic which is a product of a calculated value of a time of three-phase output voltages in a state where a positive bus, a negative bus, and a neutral line are connected respectively to three-phase phase output terminals, and a predicted neutral current value in the state; and second and third calculated values icx and icy which are products of a calculated value of a time of the three-phase output voltages that can take state 1 where two of the three-phase phase output terminals are connected to the positive bus or the neutral line, and a remaining one terminal is connected to the neutral line or the negative bus, and state 2 opposite to the state, and predicted neutral current values in states 1 and 2, a time ratio of state 1 and 2 during a PWM period is determined so as to make a current flowing through the neutral line close to zero, or a potential of the neutral line of the three-phase output voltages close to a voltage which is exactly the middle between voltages of the positive and negative busses.

TECHNICAL FIELD

The present invention relates to a three-level neutral-point-clamped PWMinverter apparatus which is one of a power converter such as an inverteror a servo drive that speed-variably drives a motor, and a powerconverter that interconnects systems, and also to a neutral voltagecontroller which is used in such a three-level neutral-point-clamped PWMinverter to control a neutral voltage that is a voltage between aneutral point of two capacitors connected in series between positive andnegative busses of the apparatus, and the negative bus.

BACKGROUND ART

FIG. 1 is a circuit diagram showing the main circuit configuration of athree-level neutral-point-clamped PWM inverter apparatus. As shown inFIG. 1, the three-level neutral-point-clamped PWM inverter apparatus isconfigured by two capacitors 7, three-phase output terminals, twelveswitching elements 8, and eighteen diodes 9.

In the thus configured three-level neutral-point-clamped PWM inverterapparatus, when switching elements 8 ₁, 8 ₂ are turned on, the outputterminals of the phases are connected to a positive bus which isconnected to a point P, and output phase voltages of the phases are at ahigh level. When switching elements 8 ₂, 8 ₃ are turned on, the outputterminals of the phases are connected to a point C which is the neutralpoint, and the output phase voltages of the phases are at anintermediate level (neutral voltage) which is between the high level anda low level. When switching elements 8 ₃, 8 ₄ are turned on, the outputterminals of the phases are connected to a negative bus which isconnected to a point N, and the output phase voltages of the phases areat the low level. In the three-level neutral-point-clamped PWM inverterapparatus, usually, the switching elements 8 are switched on the basisof the above-mentioned three patterns to drive a three-phase load.

In such a three-level neutral-point-clamped PWM inverter apparatus, theneutral voltage is obtained by voltage division of the capacitors 7. Theneutral voltage is varied in accordance with a current supplied to theload. When the neutral voltage is varied, an excess voltage is appliedto the capacitors 7, thereby causing the possibility that the capacitors7 are shortened in life or broken. In a three-levelneutral-point-clamped PWM inverter apparatus, therefore, a neutralvoltage control is performed in order to suppress or control variationof the neutral voltage.

In a neutral voltage control of the thus configuredneutral-point-clamped PWM inverter, conventionally, the current flowingthrough the neutral line is controlled by using dipolar modulation orunipolar modulation as a method of generating PWM pulses, and increasingand decreasing the zero-sequence voltage of a voltage command.

On the other hand, as disclosed in JP-A-5-292754, when the concept of avoltage vector is introduced and a PWM control is performed, a method isusually employed in which a neutral voltage control is performed whilethe increasing or decreasing direction of an intermediate voltage vectoris determined from the sign of a load power. As proposed inJP-A-2001-57784, such a method includes that in which a generation timeratio of a correction vector is finely adjusted in accordance with thedirection of a current flowing through a neutral line.

In these methods, variation of the neutral voltage is suppressed by,among twelve sets of switch states such as shown in FIG. 2, adjustingthe ratio of paired switch states in which the output voltages are equalto each other but the current directions of the neutral line areopposite to each other.

As proposed in JP-A-2001-61283, there is also a method such as shown inFIG. 3 in which a switch state disturbing the neutral voltage issuppressed. When switch states which can be attained by aneutral-point-clamped PWM inverter are indicated in the form of outputvoltage vectors, they can be expressed as shown in FIG. 4.

FIG. 5 shows an example of an apparatus which calculates a PWM pulse ofa neutral-point-clamped PWM inverter with using the concept of a spacevoltage vector. The apparatus comprises a vector time calculator 102, avector time register 103, a PWM pulse pattern setting device 104, and aparameter setting device 105.

In the apparatus, it is assumed that an output voltage output from theinverter is a space vector quantity such as shown in FIG. 4. When themodulation rate (k) and phase (θ) of an output voltage V are given, thevector time calculator 102 outputs the region of the output voltagevector V to the PWM pulse pattern setting device 104, selects the 27kinds of vectors shown in FIG. 4, and calculates vector sequences whichare sequentially output and vector output times (T0-T5) as PWM pulses inwhich an average of PWM periods is equal to the output voltage vector V.The vector sequences and the vector output times (T0-T5) are stored inthe vector time register 103. The vector sequences and vector outputtimes which are stored are converted by the PWM pulse pattern settingdevice 104 to a pulse sequence of U1, U2, V1, V2, W1, and W2 which driveswitch elements of an inverter main circuit. The switch elements of theinverter main circuit are turned on/off by the pulse sequence, and adesired voltage is output. In this apparatus, on the basis of theneutral voltage from the parameter setting device 105 and a signal froma detector for a load power factor, the PWM pulse pattern setting device104 adjusts the generation time of the correction vector in a directionalong which the variation of the neutral voltage is reduced.

JP-A-9-37592 discloses a method of PWM controlling a three-levelinverter in which a region between one long vector of output spacevectors of a three-level inverter, and a vector that is adjacent to thelong vector, and that has an intermediate length is set as one space.The whole space of 360° which is formed by these vectors is divided intotwelve regions. The region number of a command vector in the twelveregions is judged depending on the rotation angle of the command vector.The modulation rate is calculated in accordance with the degree of thecommand vector. The transmission system and the transmission sequencefor suppressing variation of the neutral voltage of voltage dividingcapacitors of the three-level inverter are determined in accordance withthe modulation rate and the current ratio. Specific output times of thevectors in the transmission system and the transmission sequence arecalculated to PWM control the three-level inverter.

As described above, in a three-phase neutral-point-clamped PWM inverter,usually, an even number of capacitors are directly connected betweenpositive and negative busses of a main circuit in order to obtain theneutral voltage, and a neutral line is used while being taken out from acapacitor terminal which has a voltage that is exactly the middlevoltage between the positive and negative busses. The neutral line isconnected as shown in FIGS. 2 and 3 depending on the output load of thePWM inverter and the switch states of the PWM inverter. The voltage ofthe neutral line (the neutral voltage) is varied in accordance with thecurrent which charges the capacitors through the positive and negativebusses, and that which is supplied from the connected load.

As shown in the conventional art examples, in the switch states shown inFIG. 3 (in the description, the vector is referred to as a correctionvector), a set of switch states in which the line voltage to be outputto the load is the same but the phase of the load connected to theneutral line is different (adjacent switch states in FIG. 2 are bundledinto one set) is used, and the time ratio in which the switch states ofthe set are generated is adjusted, whereby the neutral potential can befinely controlled.

In the switch states shown in FIG. 2 (in the description, the vector isreferred to as an intermediate vector), however, the neutral voltage isvaried by the phase currents of the load connected to the neutral lineand the time ratio in which the switch state is generated, and there isno vector which corrects the variation. Therefore, the variation of theneutral voltage caused by an intermediate vector must be corrected withusing a correction vector.

As shown in JP-A-2-261063, therefore, a zero-sequence voltage is addedto the modulation rate, the occurrence time of a correction vector isadjusted, and the variation of the neutral voltage is controlled withoutchanging the output line voltage which is to be supplied to a load. Asshown in JP-A-5-292754 and JP-A-2001-57784, also in the method whichuses the concept of a space voltage vector, an output is conducted sothat a correction vector is used in a voltage vector to be used, and theoccurrence time of the switch state of the set is adjusted to controlthe neutral voltage. In these methods, however, the technique ofdetermining the ratio of the correction vector to make the neutralvoltage variation close to zero is not optimum, and the effect ofsuppressing the neutral voltage variation is insufficient.

In the method described in JP-A-9-37592, the transmission system and thetransmission sequence for suppressing variation of the neutral potentialof the voltage dividing capacitors of the predetermined three-levelinverter are determined in accordance with the modulation rate and thecurrent ratio, and specific output times of the vectors in thetransmission system and the transmission sequence are calculated toperform a PWM control. Therefore, it is possible to bring the neutralcurrent close to zero. In the method also, however, the neutral voltagevariation cannot be reduced completely to zero.

FIG. 6 is a block diagram showing the configuration of a conventionalneutral voltage controller which detects the level of the neutralvoltage and outputs a neutral voltage control command for suppressingthe neutral voltage variation. As shown in FIG. 6, the conventionalneutral voltage controller is configured by two isolation amplifiers 6and a calculation circuit 3.

A first reference voltage V_(ref1) which is one half of a voltage V_(PN)(DC bus voltage) between the point P and the point N, and a voltagebetween the point C and the point N, i.e., the neutral voltage V_(CN)are input to the two isolation amplifiers 6, respectively. Thecalculation circuit 3 receives outputs of the two isolation amplifiers6, calculates a neutral voltage control command for making the neutralvoltage VCN and the first reference voltage V_(ref1) coincident witheach other, and outputs the command. The neutral voltage control commandis a command to produce an output pattern of a PWM (Pulse WidthModulation) command for raising or lowering the value of the neutralvoltage.

As described above, in the neutral voltage controller, the neutralvoltage VCN and the first reference voltage V_(ref1) are input to thecalculation circuit 3, and hence the two isolation amplifiers 6 servingas insulation circuits are required. Such insulation circuits arerequired because the calculation circuit 3 is usually driven by a powersource which is different from that for the main circuit of theinverter.

However, the isolation amplifiers 6 are expensive analog insulationcircuits having a wide linear characteristic, and therefore have aproblem in that the neutral voltage controller is expensive. In theconventional neutral voltage controller, since the calculation circuit 3controls the neutral voltage on the basis of analog signals, there is aproblem in that the apparatus is easily affected by noises or the like.

DISCLOSURE OF THE INVENTION

It is an object of the invention to provide a three-phaseneutral-point-clamped PWM inverter apparatus in which the neutralpotential variation can be efficiently suppressed, and the safety andthe quality of the output voltage can be improved.

In order to attain the object, in the three-phase neutral-point-clampedPWM inverter apparatus of the invention, a first calculated value whichis a product of: a calculated value of a time of three-phase outputvoltages in a state where a positive bus, a negative bus, and a neutralline are connected respectively to three-phase phase output terminals;and a predicted neutral current value in the state is obtained.Moreover, second and third calculated values which are products of: acalculated value of a time of the three-phase output voltages that cantake state 1 where two of the three-phase phase output terminals areconnected to the positive bus or the neutral line, and a remaining oneterminal is connected to the neutral line or the negative bus, and state2 opposite to the state; and predicted neutral current values in states1 and 2 are obtained. Furthermore, on the basis of the first, second,and third calculated values, a time ratio of state 1 and 2 during a PWMperiod is determined so as to make a current flowing through the neutralline close to zero, or a potential of the neutral line of thethree-phase output voltages close to a potential which is exactly themiddle between voltages of the positive and negative busses.

According to the configuration, the neutral potential variation can beefficiently suppressed by making close to zero as far as possible, ormaking the potential of the neutral line close to a potential which isexactly the middle between the potentials of the positive and negativebusses. Therefore, the safety and the quality of the output voltage canbe improved.

It is another object of the invention to provide a neutral voltagecontroller which is economical, and highly reliable and accurate.

In order to attain the object, in the invention, a first referencevoltage value which is one half of a voltage between a positive bus anda negative bus is subtracted from a value of a neutral voltage, when aresult of the subtraction is smaller than a second reference voltagevalue which is a negative value, a signal for raising the neutralvoltage is turned on, when the result of the subtraction is larger thana third reference voltage value which is a positive value, a signal forlowering the neutral voltage is turned on, the two signals are convertedin an insulative manner to a 2-bit digital signal, and a neutral voltagecontrol command is calculated on the basis of the digital signal andthen output.

According to the configuration, the differences between the neutralvoltage and the reference voltage values are expressed by a digitalsignal instead of an analog signal, thereby enabling economicalinsulating means to be used without using expensive insulating meanshaving a wide linear characteristic. Therefore, the whole apparatus canbe economically configured. Since the differences between the neutralvoltage and the reference voltage values are processed in the form of adigital signal instead of an analog signal, an influence of noises on aninput to calculating means can be reduced. Therefore, it is possible toprovide a neutral voltage controller in which the reliability isenhanced, and which is highly accurate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a main circuit configuration of athree-level inverter apparatus;

FIGS. 2(a) to 2(l) shows the diagrams showing an example of sets ofswitch states of a three-phase neutral-point-clamped inverter;

FIGS. 3(a) to 3(f) show the diagrams showing an example of other sets ofswitch states of the three-phase neutral-point-clamped inverter;

FIG. 4 is a diagram of output voltage space vectors of a three-phaseneutral-point-clamped inverter;

FIG. 5 is a block diagram of a conventional PWM pulse calculationcircuit;

FIG. 6 is a block diagram showing the configuration of a conventionalneutral voltage controller;

FIG. 7 is a block diagram showing the configuration of a PWM pulsecalculator of a three-phase neutral-point-clamped inverter of a firstembodiment of the invention;

FIG. 8 is a block diagram showing the configuration of a neutral voltagecontroller of a second embodiment of the invention;

FIG. 9 is a view showing an operation of a neutral voltage controller ofa third embodiment of the invention; and

FIG. 10 is a block diagram showing the configuration of the neutralvoltage controller of the third embodiment of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the invention will be describedwith reference to the drawings. In the drawings, the same referencenumerals denote the identical components.

First Embodiment

Next, a three-phase neutral-point-clamped PWM inverter apparatus of afirst embodiment of the invention will be described with reference toFIG. 7. FIG. 7 is a block diagram showing the configuration of a PWMpulse calculator of a three-phase neutral-point-clamped inverterapparatus of the embodiment. As shown in FIG. 7, the three-phaseneutral-point-clamped inverter apparatus of the embodiment comprises aneutral potential control parameter calculator 101, a vector timecalculator 102, a vector time register 103, and a PWM pattern settingdevice 104.

When the three-phase neutral-point-clamped inverter apparatus of theembodiment is to output an output voltage vector V, PWM pulses areoutput on the basis of vectors constituting the regions (regions 1 to 6)where the output voltage vector V exists, shown in FIG. 4. Assuming thatthe vectors constituting the regions are sorted as shown in FIG. 4, thevector time calculator 102 calculates total output times of the sortedvectors to output the output voltage vector V, as follows:

total output time of zero-voltage vector T0 total output time of xp andxn vectors T1 total output time of z vector T2 total output time of ypand yn vectors T3 total output time of a vector T4 total output time ofb vector T5.

The currents of the neutral line due to outputs of the vectors areindicated as follows:

neutral current due to output of z vector: ic

neutral current due to output of xp and xn vectors: icx

neutral current due to output of yp and yn vectors: icy.

Measured values of U-, V-, and W-phase load current instantaneous valuesare indicated by i(U), i(V), and i(W), respectively. When the vectorsare in the respective regions, i(phase1), i(phase2), and i(phase3) arechanged respectively to i(U), i(V), and i(W) as shown in Table 2.Therefore, the neutral currents can be calculated by the followingexpressions. In the expressions, phase1 is the phase when xp and xnvectors are output, phase2 is the phase when z vector is output, andphase3 is the phase when yp and yn vectors are output.

ic=i(phase2)×T2

icx=i(phase1)×T1

 icy=i(phase3)×T3

When the neutral currents ic, icx, and icy are obtained in this way, theneutral potential variation can be made close to zero be determining thetime ratios of xp and xn, and yp an yn vectors so that the currentvariation of the neutral line is made close to zero by using ic, icx,and icy.

Hereinafer, an example of a specific method of calculating the timeratios of the vectors will be described.

As described in JP-A-2001-57784, the parameter setting device 105 usesneutral potential control parameters (α, α1, and α2 in the neutralpotential control. Relationships among the parameters are changeddepending on relationships between the region where the voltage vectorexists and the phase currents in the following manner:

when i(phase1)≧0, α1=α

when i(phase1)<0, α1=1−α

when i(phase3)≧0, α2=1−α

when i(phase3)<0, α2=α

(Note: a phase current which is directed from the inverter to a motor ispositive.)

Table 1 below shows the correspondence among phase1, phase2, and phase3,and the U-, V-, and W-phases.

TABLE 1 Correspondence Table of Phases Region phase1 phase2 phase3 1 U VW 2 V U W 3 V W U 4 W V U 5 W U V 6 U W V

Then, the time allocations of xp and xn vectors are set as follows:

time of xp vector: Txp=α1×T2

time of xn vector: Txn=(1−α1)×T2,

and the time allocations of yp and yn vectors are set as follows:

time of yp vector: Typ=α2×T3

time of yn vector: Tyn=(1−α2)×T3.

The neutral potential control parameter α is calculated by a neutralpotential control parameter calculator 106 as a sum of two parameters α′and α″ as follows:

α=α′+α″ (0≦α≦1).

It is assumed that α is limited to a range of 0 or more to 1 or less.

Here, α′ is calculated in the following manner:

D=γ/(2×β)

α′=D (when ic≧0)

α′=−D (when ic<0)

(also α′ is limited to a range of 0 or more to 1 or less).

Furthermore, α″ is an offset adjustment parameter, and assumed to beused for compulsively controlling the neutral potential in the case ofan abnormal neutral potential or the like, and to be usually 0.5.

Moreover, β and γ are obtained in the manner shown in (1) to (4) below.

(1) When |ic|<|icx|≦|icy| or |ic|<|icy|≦|icx|, α′ is calculated whilesetting γ=ic and β=|icx|+|icy|.

(2) When |icx|≦|ic|≦|icy| or |icx|≦|icy|≦|ic|, α′ is calculated whilesetting γ=|ic|−|icx| and β=|icy|.

However, α1 is separately set in the following manner:

when icx and ic have the same sign,

α1=1 is fixed, and

when icx and ic have different signs,

α1=0 is fixed.

(3) When |icy|≦|ic|≦|icx| or |icy|≦|icx|≦|ic|, α′ is calculated whilesetting γ=|ic|−|icy| and β|icx|.

However, α2 is separately set in the following manner:

when icx and ic have the same sign,

α2=0 is fixed, and

when icy and ic have different signs,

α2=1 is fixed.

(4) When |icx|+|icy|≦|ic|,

when icx and ic have the same sign,

α1=1 is fixed,

when icx and ic have different signs,

α1=0 is fixed,

when icy and ic have the same sign,

α2=0 is fixed, and

when icy and ic have different signs,

α2=1 is fixed.

When the neutral potential control parameter α is calculated in thisway, the neutral potential variation due to the neutral current which iscaused to flow by z vector can be made close to zero as far as possiblefor each PWM period, by efficiently using the neutral current which iscaused to flow by xp, xn, yp, and yn vectors.

Also in the method in which generation of z vector is suppressed as inthe method described in JP-A-2001-061283, when T2 in the abovecalculation is set as the time elapsed after generation of the vector issuppressed, the neutral potential variation can be efficientlysuppressed while maintaining the above calculation as it is.

In the three-phase neutral-point-clamped PWM inverter apparatus of theembodiment, in consideration of the case where ic is so large thatcompensation cannot be completely attained during the PWM perioddepending on the operation conditions of the inverter, such as the caseof |icx|+|icy|≦|ic|, compensation is performed in a slightly excessivedegree when

|icx|+|icy|≧|ic|, |icx|≧|ic|, and |icy|≧|ic|

are caused.

In order to realize the above, in the three-phase neutral-point-clampedPWM inverter apparatus of the embodiment, a change may be made so as tocompensate the integral value of a current which has flown through theneutral line up to now, instead of compensation of the neutral currentwhich is caused to flow by z vector during a PWM period. Specifically, achange may be made so that ic uses a sum of a time integral value ic0 ofa neutral current which has flown before the previous period, and theneutral current i(phase2) caused by z vector in the next PWM period, asindicated by the following expression:

ic=ic0+i(phase2)×T2.

According to the configuration, it is possible to suppress the neutralpotential variation which has not been sufficiently suppressed duringone period. The time integral value ic0 of the neutral current may bemeasured by a current sensor disposed on the neutral line, or calculatedby prediction based on the phase output currents coupled to the neutralline.

In the case where the capacitances of series-connected smoothingcapacitors are equal to one another, when the neutral current is madeclose to zero as in the three-phase neutral-point-clamped PWM inverterapparatus of the embodiment, the neutral potential variation can be madezero, and the neutral potential can be controlled to the potential (thepotential is indicated by V0) which is exactly the middle between thepotentials of the positive and negative busses. In the case where thecapacitances of the series-connected capacitors are made different fromone another as a result of deterioration with time, even when theneutral current is made close to zero, however, the neutral potentialcannot be controlled to become the potential which is exactly the middlebetween the potentials of the positive and negative busses.

In the invention, therefore, instead that the neutral current is madeclose to zero from the calculated values of ic, icx, and icy, theneutral current may be controlled so that the currently is converselyincreased so as to be close to V0. In this case, the neutral potentialcontrol parameter calculator 101 detects the level of the neutralpotential. If the potential is higher than V0, the neutral current canbe increased from the calculated values of ic, icx, and icy in thedirection of the arrow in FIG. 1, and, if the potential is lower thanV0, the neutral current can be increased in the direction opposite tothat of the arrow in FIG. 1.

Second Embodiment

The second neutral voltage controller of the invention will bedescribed. FIG. 8 is a block diagram showing the configuration of theneutral voltage controller of the embodiment. As shown in FIG. 8, theneutral voltage controller of the embodiment is configured by asubtracter 1, two comparators 2, a calculation circuit 3, and insulationcircuits 10.

The subtracter 1 outputs a value which is obtained by subtracting thefirst reference voltage V_(ref1) from the neutral voltage V_(CN). Asdescribed above, the first reference voltage value V_(ref1) is one half(½·V_(PN)) of the voltage between the point P and the point N.

In the neutral voltage controller of the embodiment, in addition to thefirst reference voltage value V_(ref1), a second reference voltage valueV_(ref2) and a third reference voltage value V_(ref3) are used. As shownin FIG. 9, the second reference voltage value V_(ref2) and the thirdreference voltage value V_(ref3) are negative and positive values,respectively.

One of the comparators 2 turns on a signal for raising the neutralvoltage and outputs the signal to the calculation circuit 3 when thevalue of the output of the subtracter 1 is smaller than the secondreference voltage value V_(ref2). The other comparator 2 turns on asignal for lowering the neutral voltage V_(CN) and outputs the signal tothe calculation circuit 3 when the value of the output of the subtracter1 is larger than the third reference voltage value V_(ref3).

The signals output from the two comparators 2 are input to theinsulation circuits 10 as a 2-bit digital signal, and then input to thecalculation circuit 3. Since the insulation circuits 10 are circuitswhich handle a digital signal, the circuits are not required to have alinear characteristic and the like in a wide range. Therefore, theinsulation circuits can be configured more economically than theisolation amplifiers 6 shown in FIG. 2.

The calculation circuit 3 receives the outputs of the two comparators 2.When the signals from the two comparators 2 are not input, the circuitmaintains the neutral voltage as it is. When the signal for raising theneutral voltage is input, the circuit produces a neutral voltage controlcommand for raising the neutral voltage. When the signal for loweringthe neutral voltage is input, the circuit produces a neutral voltagecontrol command for lowering the neutral voltage.

As described above, in the neutral voltage controller of the embodiment,the differences between the neutral voltage V_(CN) and the referencevoltage values are converted from the analog signals to a digitalsignal. Therefore, the economical insulation circuits 10 which handle adigital signal can be used without using expensive insulation circuitshaving a wide linear characteristic. As a result, the whole apparatuscan be economically configured.

In the neutral voltage controller of the embodiment, the differencesbetween the neutral voltage V_(CN) and the reference voltage values areprocessed in the form of a digital signal instead of an analog signal.Therefore, an influence of noises on the input to the calculationcircuit 3 can be reduced, so that the reliability of the apparatus canbe enhanced, and a highly accurate neutral voltage control is enabled.

In the neutral voltage controller of the embodiment, a dead band isdisposed with using the second reference voltage value V_(ref2) and thethird reference voltage value V_(ref3) as thresholds, thereby allowingthe neutral voltage control to be performed without being affected bynoises of a small level which are contained in the neutral voltage. Inthe neutral voltage controller of the embodiment, moreover, it ispreferable to set the thresholds due to the second reference voltagevalue V_(ref2) and the third reference voltage value V_(ref3) so as tobe wider the neutral voltage variation which occurs at a frequency thatis three times the frequency output by the three-level inverterapparatus. According to the configuration, the influence of noises canbe eliminated, and a usual variation component, i.e., a variationcomponent of a frequency which is thrice the operation frequency can beneglected. Therefore, simplification and high reliability of the controlcan be realized. The calculation circuit 3 may be configured bysoftware, or by hardware such as an electric circuit.

Third Embodiment

Next, a neutral voltage controller of a third embodiment of theinvention will be described with reference to FIG. 10. FIG. 10 is ablock diagram showing the configuration of the neutral voltagecontroller of the embodiment. As shown in FIG. 10, the neutral voltagecontroller of the embodiment is different from the neutral voltagecontroller of the above-described embodiment in that the controllercomprises a comparator 4 in place of the two comparators 2, and astorage device 5 instead of the calculation circuit 3.

The comparator 4 receives a value which is obtained by subtracting thefirst reference voltage V_(ref1) from the neutral voltage V_(CN), andoutputs three 2-bit digital signals which have different values in caseswhere the value of the output of the subtracter 1 is smaller than thesecond reference voltage value V_(ref2), where the output value is equalto or larger than the second reference voltage value V_(ref2) and equalto or smaller than the third reference voltage value V_(ref3), and wherethe output value is larger than the third reference voltage valueV_(ref3).

The storage device 5 stores a plurality of tables of sets of values ofthe digital signals and neutral voltage control commands which are to beoutput at the values, in accordance with a motoring/regenerativeoperation of the inverter, or the operation status of the inverteraccording to the use status. The storage device 5 selects a tableaccording to the present operation status, from the tables, and outputsa neutral voltage control command corresponding to a digital signal,with using the table.

Table 2 shows switching states and changes of the neutral voltage. Theswitching states are switching patterns in the case where a vector is tobe output, such as shown in FIG. 4, and indicated in the sequence of theU-, V-, and W-phases. P indicates a state where the phase is connectedto point P on the positive side, N indicates a state where the phase isconnected to point N on the negative side, and O indicates a state wherethe phase is connected to neutral point C.

As apparent from FIG. 4, for example, ap vector and an vector areequivalent to each other as a line voltage to be output, but aredifferent in switching state. With respect to a change of the neutralvoltage in a motoring operation, for example, the change in the case ofap vector is rising, and that in the case of an vector is lowering, orthe changes are opposite to each other. Also in motoring andregenerative operations, the changes of the neutral voltage are oppositeto each other. In this way, there are sets of voltage vectors in which,even when the line voltage to be output is identical, the neutralvoltage can be raised or lowered. Depending on which vector is selected,therefore, the neutral voltage can be controlled. In the neutral voltagecontroller of the embodiment, these relationships are stored in form ofa table, so that, with respect to variation of the neutral voltage, apattern which cancels the variation can be selected.

TABLE 2 Change of Voltage Switching neutral voltage vector stateMotoring Regenerative 0p PPP Unchanged Unchanged 0o 000 UnchangedUnchanged 0n NNN Unchanged Unchanged a PNN, NPN, NNP Unchanged Unchangedb PPN, NPP, PNP Unchanged Unchanged c P0N, 0PN, NP0, Depending DependingN0P, 0NP, PN0 on phase on phase ap P00, 0P0, 00P Raising Lowering bpPP0, 0PP, P0P Raising Lowering an 0NN, N0N, NN0 Lowering Raising bn 00N,N00, 0N0 Lowering Raising

What is claimed is:
 1. A three-phase neutral-point-clamped PWM inverterapparatus which has a positive bus, a negative bus, and a neutral line,and in which neutral-point-clamped PWM inverters for three phases aredisposed, each of said neutral-point-clamped PWM inverters beingconfigured by: connecting in series first and second switch elements,and third and fourth switch elements between said positive bus and aphase voltage output terminal, and said negative bus and a phase outputterminal, respectively; and connecting a node between said first andsecond switch elements, and a node between said third and fourth switchelements to said neutral point via respective clamp elements,characterized in that said apparatus comprises: means for obtaining afirst calculated value which is a product of: a calculated value of atime of three-phase output voltages in a state where said positive bus,said negative bus, and said neutral line are connected respectively tosaid three-phase phase output terminals during a PWM period; and a valueof a current which is predicted to flow through said neutral point insaid state; means for obtaining a second calculated value which is aproducts of: a calculated value of a time of three-phase output voltagesthat can take a second state where two of said three-phase phase outputterminals are connected to said positive bus, and one of saidthree-phase phase output terminals is connected to said neutral line, ora third state where two of said three-phase phase output terminals areconnected to said neutral line, and one of said three-phase phase outputterminals is connected to said negative bus; and a value of a currentwhich is predicted to flow through said neutral line in said state;means for obtaining a third calculated value which is a products of: acalculated value of a time of three-phase output voltages that can takea fourth state where one of said three-phase phase output terminals isconnected to said positive bus, and two of said three-phase phase outputterminals are connected to said neutral line, or a fifth state where oneof said three-phase phase output terminals is connected to said neutralline, and two of said three-phase phase output terminals are connectedto said negative bus; and a value of a current which is predicted toflow through said neutral line in said state; and ratio determiningmeans for determining ratios of said second and third states, and saidfourth and fifth states during a PWM period so as to, on the basis ofsaid first, second, and third calculated values, make a current flowingthrough said neutral line close to zero, or a potential of said neutralline close to a potential which is exactly a middle between potentialsof said positive and negative busses.
 2. A three-phaseneutral-point-clamped PWM inverter apparatus according to claim 1,wherein, in place of said ratio determining means set froth in claim 1,ratio determining means obtains a fourth calculated value which is a sumof said first calculated value, and an integral value of a current whichhas flown through said neutral line up to a PWM period preceding by oneperiod, and determines ratios of said second and third states, and saidfourth and fifth states during a PWM period so as to, on the basis ofsaid second and third calculated values, make said fourth calculatedvalue close to zero, or, with using said fourth calculated value, apotential of said neutral line close to a potential which is exactly amiddle between potentials of said positive and negative busses.
 3. Athree-phase neutral-point-clamped PWM inverter apparatus according toclaim 1, wherein, in a three-phase neutral-point-clamped PWM inverterapparatus in which a time of three-phase output voltages in six switchstates where said positive bus, said negative bus, and said neutral lineare connected respectively to said three-phase phase output terminals issuppressed to a first preset value or smaller, and an insufficientamount of an output voltage is compensated six switch states where eachof said three-phase phase output terminals is connected to said positivebus or said negative bus, and excluding a state where all of three ofsaid three-phase phase output terminals are concurrently connected tosaid positive bus or said negative bus, in place of said means forobtaining said first calculated value set froth in claim 1, meansobtains a first calculated value which is a product of: the time ofthree-phase output voltages which are suppressed to said first presetvalue or smaller during a PWM period; and a value of a current which ispredicted to flow through said neutral point in said state.
 4. Athree-phase neutral-point-clamped PWM inverter apparatus according toclaim 3, wherein a measured value of a current flowing through saidneural line is used in place of said current which is predicted to flowthrough said neutral point, and said ratio determining means obtains afourth calculated value which is a sum of said first calculated value,and an integral value of a current which has flown through said neutralline up to a PWM period preceding by one period, and determines ratiosof said second and third states, and said fourth and fifth states duringa PWM period so as to, on the basis of said second and third calculatedvalues, make said fourth calculated value close to zero, or, with usingsaid fourth calculated value, a potential of said neutral line close toa potential which is exactly a middle between potentials of saidpositive and negative busses.
 5. A three-phase neutral-point-clamped PWMinverter apparatus according to any one of claims 1 to 3, wherein, insaid means for obtaining said first to third calculated values, saidvalue of said current which is predicted to flow through said neutralpoint is calculated by using a value of a current which is predicted toflow through said phase output terminal connected to said neutral line.6. A neutral voltage controller which controls a neutral voltage that isa voltage between a neutral point of two capacitors connected in seriesbetween positive and negative busses of a three-level inverterapparatus, and said negative bus, characterized in that said neutralvoltage controller comprises: subtracting means for outputting a valuewhich is obtained by subtracting a first reference voltage value from avalue of said neutral voltage, said first reference voltage value beingone half of a voltage between said positive and negative busses; firstcomparing means for, when said value output from said subtracting meansis smaller than a second reference voltage value which is a negativevalue, turning on a signal for raising said neutral voltage; secondcomparing means for, when said value output from said subtracting meansis larger than a third reference voltage value which is a positivevalue, turning on a signal for lowering said neutral voltage; insulatingmeans for converting said two signals to a 2-bit digital signal in aninsulative manner; and calculating means for, on the basis of saiddigital signal, calculating a neutral voltage control command, andoutputting said command.
 7. A neutral voltage controller which controlsa neutral voltage that is a voltage between a neutral point of twocapacitors connected in series between positive and negative busses of athree-level inverter apparatus, and said negative bus, characterized inthat said neutral voltage controller comprises: subtracting means foroutputting a value which is obtained by subtracting a first referencevoltage value from a value of said neutral voltage, said first referencevoltage value being one half of a voltage between said positive andnegative busses; a comparator which outputs a 2-bit digital signalhaving different values in cases where said value output from saidsubtracting means is smaller than a second reference voltage value whichis a negative value, where said value output from said subtracting meansis larger than a third reference voltage value which is a positivevalue, and where said value output from said subtracting means is equalto or larger than said second reference voltage value and equal to orsmaller than said third reference voltage value; insulating means foroutputting said bit digital signal in an insulative manner; andcalculating means for, on the basis of said digital signal, calculatinga neutral voltage control command, and outputting said command.
 8. Aneutral voltage controller which controls a neutral voltage that is avoltage between a neutral point of two capacitors connected in seriesbetween positive and negative busses of a three-level inverterapparatus, and said negative bus, characterized in that said neutralvoltage controller comprises: subtracting means for outputting a valuewhich is obtained by subtracting a first reference voltage value from avalue of said neutral voltage, said first reference voltage value beingone half of a voltage between said positive and negative busses; firstcomparing means for, when said value output from said subtracting meansis smaller than a second reference voltage value which is a negativevalue, turning on a signal for raising said neutral voltage; secondcomparing means for, when said value output from said subtracting meansis larger than a third reference voltage value which is a positivevalue, turning on a signal for lowering said neutral voltage; insulatingmeans for converting said two signals in an insulative manner to a 2-bitdigital signal; and storage means for previously storing a table of setsof a value of said digital signal and a neutral voltage control commandwhich is to be output at said value, obtaining a neutral voltage controlcommand which corresponds to said digital signal supplied from saidinsulating means, from said table, and outputting said neutral voltagecontrol command.
 9. A neutral voltage controller which controls aneutral voltage that is a voltage between a neutral point of twocapacitors connected in series between positive and negative busses of athree-level inverter apparatus, and said negative bus, characterized inthat said neutral voltage controller comprises: subtracting means foroutputting a value which is obtained by subtracting a first referencevoltage value from a value of said neutral voltage, said first referencevoltage value being one half of a voltage between said positive andnegative busses; a comparator which outputs a 2-bit digital signalhaving different values in cases where said value output from saidsubtracting means is smaller than a second reference voltage value whichis a negative value, where said value output from said subtracting meansis larger than a third reference voltage value which is a positivevalue, and where said value output from said subtracting means is equalto or larger than said second reference voltage value and equal to orsmaller than said third reference voltage value; insulating means foroutputting said digital signal in an insulative manner; and storagemeans for previously storing a table of sets of a value of said digitalsignal and a neutral voltage control command which is to be output atsaid value, obtaining a neutral voltage control command whichcorresponds to said digital signal supplied from said insulating means,from said table, and outputting said neutral voltage control command.10. A neutral voltage controller according to claim 9, wherein saidstorage means stores a plurality of said tables corresponding tooperation statuses of an inverter, selects a table corresponding to apresent operation status, from said tables, and outputs a neutralvoltage control command corresponding to said digital signal with usingsaid table.
 11. A neutral voltage controller according to any one ofclaims 6 to 10, wherein a difference between said second and thirdreference voltage values is set to be larger than an amplitude ofneutral voltage variation at a frequency which is three times an outputfrequency of said three-level inverter.